The present invention relates to a method of manufacturing a semiconductor device.
Japanese Unexamined Patent Application Publication No. 2009-111380 discloses a technique by which different work function modulating elements are implanted into the respective gate stacks of a PMOS region and an NMOS region (a gate electrode and a gate insulator film).
According to this publication, a layer containing the work function modulating elements therein is formed over a gate electrode, and the layer in the PMOS region is removed through the photolithography so that only the work function modulation elements in the NMOS region remain. Subsequently, a heat treatment is conducted on the gate stacks so that the work function modulating elements are implanted into the gate stack. As a result, the different work function modulating elements are implanted into the PMOS region and the NMOS region so that the work functions of the respective gate stacks can be controlled.
Japanese Unexamined Patent Application Publication No. 2008-166713 discloses a technique by which a dielectric layer configuring a gate insulator film remains in only one of two regions through the lift-off technique.